verilog - Is this code structure going in the right direction? -

i trying utilize 7 segment display. have written module want take 4 inputs , change hex output. there seems issue unpacked/packed arrays , don't know on earth i'm doing. appreciated.

module hexdisplay(hex, c0, c1, c2, c3);     input c0;     input c1;     input c2;     input c3;           output hex[6:0];            reg out[6:0];      always@(*)     begin         case({c3, c2, c1, c0})             4'b0000:out [5:0] = 1;             // 0001-1111 go here             //...             default:out [6:0] = 0;          endcase       assign hex = out;      end  endmodule 

errors:

error (10773): verilog hdl error @ lab2pre.v(55): declaring module ports or function arguments unpacked array types requires systemverilog extensions error (10133): verilog hdl expression error @ lab2pre.v(61): illegal part select of unpacked array "out"

error (10133): verilog hdl expression error @ lab2pre.v(62): illegal part select of unpacked array "out"

error (10048): verilog hdl error @ lab2pre.v(64): values cannot assigned directly or part of array "hex" - assignments must made individual elements only

error (10137): verilog hdl procedural assignment error @ lab2pre.v(64): object "hex" on left-hand side of assignment must have variable data type

error (10044): verilog hdl error @ lab2pre.v(64): expression cannot reference entire array "out"

error: quartus ii 64-bit analysis & synthesis unsuccessful. 6 errors, 1 warning error: peak virtual memory: 959 megabytes error: processing ended: tue feb 2 17:33:35 2016 error: elapsed time: 00:00:15 error: total cpu time (on processors): 00:00:46

error (293001): quartus ii full compilation unsuccessful. 8 errors, 1 warning

2 errors :

• you need have "packed" array rather "unpacked" array "out" & "hex" nets.

  systemverilog supports both packed arrays , unpacked arrays of data. term packed array used refer dimensions declared before data identifier name. term unpacked array used refer dimensions declared after data identifier name.

  bit [7:0] c1; // packed array of scalar bit types real u [7:0]; // unpacked array of real types

  a packed array mechanism subdividing vector subfields, can conveniently accessed array elements. consequently, packed array guaranteed represented contiguous set of bits.

  an unpacked array may or may not represented. packed array differs unpacked array in that, when packed array appears primary, treated single vector.

  so in code, require, out & hex used continuous bit vector, should packed array, instead of unpacked array.

  refer topic 7.4 of systemverilog lrm.

• assign statement hex, cannot in block. because assign statement used modeling combinational logic , executed continuously. assign statement called 'continuous assignment statement' there no sensitive list.

  so can't within block, executed per sensitivity list.

so final working code below:

module hexdisplay(hex, c0, c1, c2, c3);     input c0;     input c1;     input c2;     input c3;           output [6:0] hex;            reg [6:0] out;      always@(*)     begin         case({c3, c2, c1, c0})             4'b0000:out [5:0] = 1;             // 0001-1111 go here             //...             default:out [6:0] = 0;          endcase      end      assign hex = out; endmodule